1. Field of the Invention
The invention relates generally to memory controllers and more particularly, to a pipelined memory controller with a request buffer.
2. Description of the Related Technology
A computer system relies on memory to store instructions and data that are processed by a computer system processor. Breathtaking advances have been made in both the storage capacity and speed of computer memory devices. However, the speed increases of memory devices have not been able to keep pace with the speed increases achieved with current microprocessors. As a result, the speed of current computer systems is limited by the speed in which the data instructions can be accessed from the memory of the computer system.
The typical memory contains an array of memory cells connected to each other by row and column lines. Each memory cell stores a single bit and is accessed by a memory address that includes a row address that indexes a row of the memory array and a column address that indexes a column of the memory array. Accordingly, each memory address points to the memory cell at the intersection of the row specified by the row address and the column specified by the column address.
In a typical computer system, the system processor communicates with the computer memory via a processor bus and a memory controller. For example, a central processing unit (CPU) issues a command and an address which are received and translated by the memory controller. The memory controller, in turn, applies appropriate command signals and row and column addresses to the memory device. Examples of such commands include a row address strobe (RAS), column address strobe (CAS), write enable (WE), and possibly a clock signal (CLK). In response to the commands and addresses, data is transferred between the CPU and the memory device.
The memory device typically includes a dynamic random access memory (DRAM) module such as a single in-line memory module (SIMM) or a dual in-line memory module (DIMM). The memory module typically includes one or more banks of memory chips connected in parallel such that each memory bank stores one word of data per memory address.
In an attempt to decrease memory access time, an even faster form of memory, referred to as synchronous DRAM (SDRAM), was created. SDRAM transfers data with the use of a clock signal. In contrast, typical DRAM devices are asynchronous because they do not require a clock input signal. The memory controller for synchronous devices receives the system clock signal and operates as a synchronous interface with the CPU so that data is exchanged with the CPU at appropriate edges of the clock signal.
SDRAMs offer substantial advances in DRAM operating performance, including the ability to synchronously burst data at a high data rate with automatic column-address generation, the ability to interleave between internal data banks in order to hide precharged time, and the capability to change column in addresses on each clock cycle during a burst access.
Typically SDRAMs are configured to include a pipeline. Pipelining refers to the interlinking or overlapping of input and output data and addresses of consecutive bus cycles. Pipelining increases the throughput of memory transactions. With this pipelined architecture SDRAMs can accept a new column address on every clock cycle.
As the speed of memory devices such as the SDRAM increases, other bottlenecks arise within computer systems. For example, as SDRAM devices are operated at faster clock rates, the memory controllers to which they are coupled often cannot exchange data between the CPU and the memory device quickly enough. Therefore, manufacturers have found that the memory controller itself needs to be pipelined.
In view of the above, it is apparent that manufacturers are in need of an efficient pipelined memory controller to facilitate the communication of the memory requests to the memory devices.
One aspect of the invention comprises a computer system, comprising: a memory module capable of storing digital information; and a memory controller, connected to the memory module, comprising: a request buffer for receiving and storing multiple memory requests, a decode module having a pointer to the request buffer, an addressing module having a pointer to the request buffer, and a state machine capable of updating the pointer in the decode module and the addressing module.
Another aspect of the invention comprises a system for handling a at least one memory request, comprising: a pipeline processor capable of processing the at least one memory request in a plurality of stages, wherein in a first stage, the at least one memory request for digital information is received and stored in a request buffer, wherein in a second stage the at least one memory request is decoded, wherein in a third stage the at least one memory request is sent to a memory module.